Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.

We are looking to hire a Design For Test (DFT) Engineer with a strong technical background and experience in DFT methodologies, complemented by a robust, self-motivated work ethic. The ideal candidate should also have a focus on quality and demonstrate a good understanding of the importance of production test on the success of a product. Some hands-on experience in one or more of the following areas is essential: RTL design, simulations and debugging, synthesis, STA. As a part of our team, you will have the opportunity to work on next-generation AI designs targeted for data centers applications.

Responsibilities

• Keep up with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies
• Work closely with design, verification, physical design and product engineering teams to integrate DFT requirements into the overall design process
• Define and implement DFT architecture and features for next-generation AI designs and support their verification effort
• Develop efficient DFT flows and methodology compatible with silicon design flows
• Work with 3rd party IPs to integrate the provided design into the DFT infrastructure
• Generate structural test vectors, analyze and improve test coverage
• Work with the product and test engineering teams to ensure successful silicon bring-up and help identify any silicon failures to enhance yield learning and improvement

Essential skills:

• Very good understanding of DFT components like JTAG (IEEE 1149.x), IJTAG (IEEE P1687), Core Test (IEEE P1500), SSN (Streaming Scan Network), Test Compression, OCC etc.
• Experience on developing DFT specifications and driving the implementation of the DFT features
• Experience in MBIST and BISR implementation and verification is desired
• Solid understanding of design verification methodologies for validating the DFT features using simulation in pre-silicon designs
• Exposure to STA constraints development and analysis for DFT modes and SDF simulations would be a plus
• Experience in Scan based testing and industry standard ATPG tools
• Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other EDA tools
• Very good knowledge of Digital Integrated Circuits and Systems
• Hands-on experience with Verilog RTL coding and familiarity with System Verilog
• Strong scripting and debugging skills using programming languages like Python, TCL, Perl, Shell etc.
• Exposure to silicon bring-up, post-silicon testing and tester pattern debugging
• Strong problem-solving skills across various levels of design hierarchies
• Great team working and communication skills

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.